Sonir.

Signal path

Nine stages, in order, with the number each one costs. Entry to DAC is 8.33 ms on the 48 kHz family and 9.71 ms on the 44.1 kHz family.

The stages

#STAGEWHAT HAPPENS
01Virtual deviceThe sending app plays into it. Blocks are 256 frames, fixed, and no volume control is published
02To the engineHanded over in shared memory. The delay is below the measurement floor
03Entry rateThe device is opened at the rate it reports. Asking for a different rate would make the system convert, and nothing on screen would look wrong
04Entry watchLevel, effective bits and stretch ratio are measured continuously and turned into a verdict
05Upsamplef32 to f64, then 16×. 48 kHz family to 768 kHz, 44.1 kHz family to 705.6 kHz. The families are never mixed
06GraphYour nodes in series plus one aux bus. Runs at the internal rate in f64, in blocks of 4,096
07A/BTwo chains are resident at once. Switching crossfades over 5 to 10 ms and carries the convolution history across
08Downsample16×, symmetric with the upsampling stage
09Output stageTrue peak measurement, auto headroom, dither and quantisation, then the DAC

Nothing in the output stage alters the signal by default. Stages 5 and 8 are the resample design, and they always carry the band limit.

Rates and precision

705.6k / 768kHz

Internal rate, 16× the incoming rate. Nyquist sits at 352.8 or 384 kHz, so harmonics from nonlinear stages do not fold back.

f64

The graph always runs in double precision. The resample stage can be set to f32.

4,096frames

Internal block length. The convolution partition matches it, so filters add no delay.

ROUNDING ERROR FLOOR
f32 (single precision)about -145 dB
f64 (what the graph uses)about -320 dB
128-bitabout -680 dB

The measured noise floor of the best DACs is around -130 dB. Double precision is already far below what any converter resolves, which is why Bench does not compete on the number of bits.

  • The families are never mixed.

    44.1 kHz material and its multiples run at 705,600 Hz; 48 kHz material and its multiples run at 768,000 Hz. A design that only works on one of them cannot be loaded, because the source can change family while playback continues.

  • The same graph loads at both rates.

    Nodes are written in Hz and dB, never in samples, so nothing has to be redesigned when the family changes. Coefficients are solved again at each rate and checked at both.

Latency

48 kHz family    8.33 ms   entry to DAC, round trip
44.1 kHz family  9.71 ms

conversion stage 0.50 ms   769 taps, linear phase, at 768 kHz
                 0.95 ms   1,345 taps, at 705.6 kHz
The factory conversion filter is linear phase, so its delay is constant across the band: pure latency, not a change in tone. A longer filter costs more of it, and the total is shown with the design.
  • Tap count does not add latency in the graph. The convolution is partitioned to the internal block length, so a long filter costs CPU rather than delay.
  • Partition length trades CPU against latency and nothing else. It does not change the sound.
  • Minimum phase in the resample design removes the bulk delay of that stage, at the cost of phase shift in the audible band.